Los Angeles: Scientists have designed the world’s first chip containing 1,000 independent programmable processors, that can compute up to 1.78 trillion instructions per second and is thought to be the fastest ever designed at a university.
The energy-efficient “KiloCore” chip contains 621 million transistors, researchers said.
“To the best of our knowledge, it is the world’s first 1,000-processor chip and it is the highest clock rate processor ever designed in a university,” said Bevan Baas, a professor at the University of California, Davis (UC Davis), who led the team that designed the chip architecture.
While other multiple processor chips have been created, none exceed about 300 processors, researchers said. Most were created for research purposes and few are sold commercially.
Each processor core can run its own small programme independently of the others, which is a fundamentally more flexible approach than the Single-Instruction-Multiple-Data approaches utilised by processors such as graphics processing unit (GPU).
The idea is to break an application up into many small pieces, each of which can run in parallel on different processors, enabling high throughput with lower energy use, Baas said.
Since each processor is independently clocked, it can shut itself down to further save energy when not needed, said Brent Bohnenstiehl, a graduate student at UC Davis, who developed the principal architecture.
Cores operate at an average maximum clock frequency of 1.78 GigaHertz, and they transfer data directly to each other rather than using a pooled memory area that can become a bottleneck for data.
The chip is the most energy-efficient “many-core” processor ever reported, Baas said.
For example, the 1,000 processors can execute 115 billion instructions per second while dissipating only 0.7 Watts, low enough to be powered by a single AA battery.
The KiloCore chip executes instructions more than 100 times more efficiently than a modern laptop processor.
Applications already developed for the chip include wireless coding/decoding, video processing, encryption, and others involving large amounts of parallel data such as scientific data applications and data centre record processing.
The team has completed a compiler and automatic programme mapping tools for use in programming the chip.
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